91C94 Datasheet, PDF (75/120 Pages) SMSC Corporation – ISA/PCMCIA SINGLE CHIP ETHERNET CONTROLLER WITH RAM

AUTO RELEASE - When set, successful
transmit packets are not written into completion
FIFO, and their memory is released
automatically.
1) One interrupt per packet: enable TX INT,
set AUTO RELEASE=0. The software driver
can find the completion result in memory and
process the interrupt one packet at a time.
Depending on the completion code the driver
will take different actions. Note that the transmit
process is working in parallel and other
transmissions might be taking place. The
LAN91C94 is virtually queuing the packet
numbers and their status words.
In this case, the transmit interrupt service
routine can find the next packet number to be
serviced by reading the TX DONE PACKET
NUMBER at the FIFO PORTS register. This
eliminates the need for the driver to keep a list
of packet numbers being transmitted. The
numbers are queued by the LAN91C94 and
provided back to the CPU as their transmission
completes.
2) One interrupt per sequence of packets:
Enable TX EMPTY INT and TX INT, set AUTO
RELEASE=1. TX EMPTY INT is generated only
after transmitting the last packet in the FIFO.
TX INT will be set on a fatal transmit error
allowing the CPU to know that the transmit
process has stopped and therefore the FIFO will
not be emptied.
This mode has the advantage of a smaller CPU
overhead, and faster memory de-allocation.
Note that when AUTO RELEASE=1 the CPU is
not provided with the packet numbers that
completed successfully.
Note: The pointer register is shared by any
process accessing the LAN91C94 memory. In
order to allow processes to be interruptable,
the interrupting process is responsible for
reading the pointer value before modifying it,
saving it, and restoring it before returning from
the interrupt.
Typically there would be three processes using
the pointer:
1) Transmit loading (sometimes interrupt
driven)
2) Receive unloading (interrupt driven)
3) Transmit Status reading (interrupt driven).
1) and 3) also share the usage of the Packet
Number Register. Therefore saving and
restoring the PNR is also required from interrupt
service routines.
POWER DOWN
The LAN91C94 can enter power down mode by
means of the PWRDWN pin (pin 68) or the
PWRDN bit (Control Register, bit 13). The
power down current is 8 mA. When in power
down mode, the LAN91C94 will:
- Stop the crystal oscillator
- Tristate: Data Bus
Interrupts
nIOCS16
10BASE-T and AUI outputs
Turn off analog bias currents
- Drive the EEPROM and ROM outputs inactive
- Preserve contents of registers and memory
The PWRDWN pin is internally gated with the
RESET (RESET pin before de-glitching) and
with the SRESET bit (COR bit 7). This gating
function internally negates power down
whenever RESET is high or SRESET is high to
allow the oscillator to run during RESET. Except
for this gating function, all other uses of the
RESET pin use a de-glitched version of the
signal as defined in the pin description section.
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