91C94 Datasheet, PDF (33/120 Pages) SMSC Corporation – ISA/PCMCIA SINGLE CHIP ETHERNET CONTROLLER WITH RAM

I/O SPACE
(ISA and PCMCIA mode)
In ISA mode, the base I/O space is determined
by the IOS0-2 inputs and the EEPROM
contents. A4-15 are compared against the base
I/O address for I/O space accesses.
In PCMCIA mode nREG (along with nIORD or
nIOWR) defines an I/O access regardless of the
A4-15 value.
OFFSET
NAME
To limit the I/O space requirements to 16
locations, the registers are assigned to different
banks. The last word of the I/O area is shared
by all banks and can be used to change the
bank in use.
Registers are 16 bits wide and are described
using the following convention:
TYPE
SYMBOL
HIGH
BYTE
BIT 15
X
BIT 14
X
BIT 13
X
BIT 12
X
BIT 11
X
BIT 10
X
BIT 9
X
BIT 8
X
LOW
BYTE
BIT 7
X
BIT 6
X
BIT 5
X
BIT 4
X
BIT 3
X
BIT 2
X
BIT 1
X
BIT 0
X
OFFSET - Defines the address offset within the
IOBASE where the register can be accessed at,
provided the bank select has the appropriate
value. The offset specifies the address of the
even byte (bits 0-7) or the address of the
complete word. The odd byte can be accessed
using address (offset + 1).
Some registers (like the Interrupt Ack., or like
Interrupt Mask) are functionally described as
two eight bit registers, in that case the offset of
each one is independently specified.
Regardless of the functional description, when
the LAN91C94 is in 16 bit mode, all registers
can be accessed as words or bytes.
The default bit values upon hard reset are
highlighted below each register.
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