91C94 Datasheet, PDF (41/120 Pages) SMSC Corporation – ISA/PCMCIA SINGLE CHIP ETHERNET CONTROLLER WITH RAM

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OFFSET
6
NAME
COUNTER REGISTER
TYPE
READ ONLY
SYMBOL
ECR
Counts four parameters for MAC statistics. When any counter reaches 15 an interrupt is issued. All
counters are cleared when reading the register and do no wrap around beyond 15.
HIGH
BYTE
NUMBER OF EXCESS DEFERRED TX
0
0
0
0
NUMBER OF DEFERRED TX
0
0
0
0
LOW
BYTE
MULTIPLE COLLISION COUNT
SINGLE COLLISION COUNT
0
0
0
0
0
0
0
0
Each four bit counter is incremented every time
the corresponding event, as defined in the EPH
STATUS REGISTER bit description, occurs.
Note that the counters can only increment once
per enqueued transmit packet, never faster,
limiting the rate of interrupts that can be
generated by the counters. For example if a
packet is successfully transmitted after one
collision the SINGLE COLLISION COUNT field
is incremented by one. If a packet experiences
between 2 to 16 collisions, the MULTIPLE
COLLISION COUNT field is incremented by
one. If a packet experiences deferral the
NUMBER OF DEFERRED TX field is
incremented by one, even if the packet
experienced multiple deferrals during its
collision retries.
The COUNTER REGISTER facilitates
maintaining statistics in the AUTO RELEASE
mode where no transmit interrupts are
generated on successful transmissions.
Reading the register in the transmit service
routine will be enough to maintain statistics.
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