91C94 Datasheet, PDF (65/120 Pages) SMSC Corporation – ISA/PCMCIA SINGLE CHIP ETHERNET CONTROLLER WITH RAM

I/O SPACE - BANK3
OFFSET
C
NAME
EARLY RCV REGISTER
TYPE
READ/WRITE
SYMBOL
ERCV
HIGH
BYTE
0
0
1
1
0
0
1
1
LOW
BYTE
RCV
DISCRD
ERCV THRESHOLD
0
0
0
1
1
1
1
1
RCV DISCRD - Set to discard a packet being
received. This bit can be used in conjunction
with ERCV THRESHOLD and ERCV INT to
process a packet header while it is being
received and discard it if the packet is not
desired. Setting this bit will only discard packets
that are still in the process of being received.
If the RCV DISCRD bit is set prior to the end of
a receive packet, RXOVRN bit in the Interrupt
Status Register will be set to indicate that the
packet was discarded and its memory
released. If the receive packet is complete prior
to the RCV DISCARD bit being set, the packet is
received normally and RCV INT bit is set in the
Interrupt Status Register. The RCV DISCARD
bit is self-clearing.
ERCV THRESHOLD - Threshold for ERCV
interrupt. Specified in 64 byte multiples.
Whenever the number of bytes written in
memory for the presently received packet
exceeds the ERCV THRESHOLD, ERCV INT bit
of the INTERRUPT STATUS REGISTER is set.
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