91C94 Datasheet, PDF (81/120 Pages) SMSC Corporation – ISA/PCMCIA SINGLE CHIP ETHERNET CONTROLLER WITH RAM

5) If AUTO_RELEASE is set, a release is
issued by the DMA block to the MMU after a
successful transmission (TX_SUCC set),
and the TX completion FIFO is clocked
together with the TX FIFO preventing the
packet number from moving into the TX
completion FIFO.
6) Based on the RX counter value, if a receive
packet exceeds 1532 bytes, reception is
stopped by the DMA and the RX ABORT bit
in the Receive Control Register is set. The
memory allocated to the packet is
automatically released.
7) If an allocation fails, the CSMA/CD block
will activate RX_OVRN upon detecting a
FIFO full condition. RXEN will stay active to
allow reception of subsequent packets if
memory becomes available.
The
CSMA/CD block will flush the FIFO upon
the new frame arrival.
PACKET NUMBER FIFOS
The transmit packet FIFO stores the packet
numbers awaiting transmission, in the order
they were enqueued. The FIFO is advanced
(written) when the CPU issues the "enqueue
packet number command", the packet number
to be written is provided by the CPU via the
Packet Number Register. The number was
previously obtained by requesting memory
allocation from the MMU. The FIFO is read by
the DMA block when the CSMA/CD block is
ready to proceed on to the next transmission.
By reading the TX EMPTY INT bit the CPU can
determine if this FIFO is empty.
The transmit completion FIFO stores the packet
numbers that were already transmitted but not
yet acknowledged by the CPU. The CPU can
read the next packet number in this FIFO from
the Fifo Ports Register. The CPU can remove a
packet number from this FIFO by issuing a TX
INT acknowledge. The CPU can determine if
this FIFO is empty by reading the TX INT bit or
the FIFO Ports Register.
The receive packet FIFO stores the packet
numbers already received into memory, in the
order they were received. The FIFO is
advanced (written) by the DMA block upon
reception of a complete valid packet into
memory. The number is determined the
moment the DMA block first requests memory
from the MMU for that packet. The first receive
packet number in the FIFO can be read via the
Fifo Ports Register, and the data associated
with it can be accessed through the receive
area. The packet number can be removed
from the FIFO with or without an automatic
release of its associated memory.
The FIFO is read out upon CPU command
(remove packet from top of RX FIFO, or remove
and release command) after processing the
receive packet in the receive area.
The width of each FIFO is 5 bits per packet
number. The depth of each FIFO equals the
number of packets the LAN91C94 can handle
(18).
The guideline is software transparency; the
software driver should not be aware of different
devices or FIFO depths. If the MMU memory
allocation succeeded, there will be room in the
transmit FIFO for enqueuing the packet.
Conversely if there is free memory for receive,
there should be room in the receive FIFO for
storing the packet number.
Note that the CPU can enqueue a transmit
command with a packet number that does not
follow the sequence in which the MMU assigned
packet numbers. For example, when a
transmission failed and it is retried in software,
or when a receive packet is modified and sent
back to the network.
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