91C94 Datasheet, PDF (72/120 Pages) SMSC Corporation – ISA/PCMCIA SINGLE CHIP ETHERNET CONTROLLER WITH RAM

TXEMPTY I NTR
Write Acknowledge Reg. with
TXEMPTY Bit Set
Read TXEMPTY & TX INTR
TXEMPTY = 0
&
TXINT = 0
(Waiting for Compl etion)
TXEMPTY = X
&
TXINT = 1
(Transmission Failed)
TXEMPTY = 1
&
TXINT = 0
(Ev erything w ent through
suc cessf ully)
Read Pkt . # Regis ter & Save
W rite Address Pointer
Regis ter
Read Statu s Word from RAM
Updat e Statistic s
I ssue "R eleas e" Comma nd
Update Variables
Ack nowledge TXI NTR
Re-Enable TXENA
R es tore Pack et Number
R eturn t oI SR
FIGURE 15 – TXEMPTY INTR
(Assumes Auto Release Option Selected)
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