91C94 Datasheet, PDF (52/120 Pages) SMSC Corporation – ISA/PCMCIA SINGLE CHIP ETHERNET CONTROLLER WITH RAM

I/O SPACE - BANK2
OFFSET
NAME
TYPE
SYMBOL
0
MMU COMMAND REGISTER
WRITE ONLY
MMUCR
BUSY bit
readable
This register is used by the CPU to control the memory allocation, de-allocation, TX FIFO and RX
FIFO control. The three command bits determine the command issued as described below:
HIGH
BYTE
LOW
BYTE
COMMAND
0
0
N2
N1
N0/BUSY
x
y
z
COMMAND SET:
xyz
000 0) NOOP - NO OPERATION
001 1)
ALLOCATE MEMORY FOR TX - N2,N1,N0 defines the amount of memory requested as
(value + 1) x 256 bytes. Namely N2,N1,N0 = 1 will request 2 x 256 = 512 bytes. Valid range
for N2,N1,N0 is 0 through 5. A shift-based divide by 256 of the packet length yields the
appropriate value to be used as N2,N1,N0. Immediately generates a completion code at the
ALLOCATION RESULT REGISTER. Can optionally generate an interrupt on successful
completion. The allocation time can take worst case (N2,N1,N0 + 2) x 200ns.
010 2) RESET MMU TO INITIAL STATE - Frees all memory allocations, clears relevant interrupts,
resets packet FIFO pointers.
011 3)
REMOVE FRAME FROM TOP OF RX FIFO - To be issued after CPU has completed
processing of present receive frame. This command removes the receive packet number
from the RX FIFO and brings the next receive frame (if any) to the RX area (output of RX
FIFO).
100 4) REMOVE AND RELEASE TOP OF RX FIFO - Like 3) but also releases all memory used by
the packet presently at the RX FIFO output.
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