91C94 Datasheet, PDF (79/120 Pages) SMSC Corporation – ISA/PCMCIA SINGLE CHIP ETHERNET CONTROLLER WITH RAM

The arbiter uses the pointer register as the CPU
provided address, and the internal DMA address
from the CSMA/CD side as the addresses to be
provided to the MMU.
I/O cycle is in progress, as the addresses could
be used for a memory cycle, or could even
glitch through a valid value. Only when nIORD
or nIOWR are activated the I/O cycle begins.
The data path routed by the arbiter goes
between memory (the data path does not go
through the MMU) on one side and either the
CPU side bus or the data path of the CSMA/CD
core.
The data path between memory and the Data
Register is in fact buffered by a small FIFO in
each direction. The FIFOs beneath the Data
Register can be read and written as bytes or
words, in any sequential combination. The
presence of these FIFOs makes sure that word
transfers are possible on the system bus even if
the address loaded into the pointer is odd.
BUS INTERFACE
In PCMCIA mode, A4-A15 are ignored for I/O
decodes, which rely on the PCMCIA host,
decoding for the slot. Input A10 for ISA is used
as an output (nFWE) for PCMCIA to enable
Flash Memory Write for programming the
attribute memory. It is valid only when nWE is
0 and COR2 is 1. nA11/nFCS is used to select
the Flash Memory Chip.
WAIT STATE POLICY
The LAN91C94 can work on most system buses
without having to add wait states. The two
parameters that determine the memory access
profile are the read access time and the cycle
time into the Data Register.
The bus interface handles the data, address and
control interfaces as a superset of the ISA and
PCMCIA specifications and allows 8 or 16 bit
adapters to be designed with the LAN91C94
with no glue to interface the ISA or PCMCIA
bus.
The functions done in this block are address
decoding for I/O and ROM memory (including
address relocation support) for ISA, data path
routing, sequential memory address support,
optional wait state generation, boot ROM
support, EEPROM setup function, bus
transceiver
control,
and
interrupt
generation/selection.
For ISA, I/O address decoding is done by
comparing A15-A4 to the I/O BASE address
determined in part by the upper byte of the
BASE ADDRESS REGISTER, and also
requiring that AEN be low. If the above address
comparison is satisfied and the LAN91C94 is in
16 bit mode, nIOCS16 will be asserted (low).
A valid comparison does not yet indicate a valid
The read access time is 40ns and the cycle time
is 185ns. If any one of them does not satisfy
the application requirements, wait states should
be added.
If the access time is the problem, IOCHRDY
should be negated for all accesses to the
LAN91C94. This can be achieved by
programming the NO WAIT ST bit in the
configuration register to 0. The LAN91C94 will
negate IOCHRDY for 100ns to 150ns on every
access to any register.
If the cycle time is the problem, programming
NO WAIT ST as described before will solve it
but at the expense of slowing down all
accesses. The alternative is to let the
LAN91C94 negate IOCHRDY only when the
Data Register FIFOs require so. Namely, if NO
WAIT ST is set, IOCHRDY will only be negated
if a Data Register read cycle starts and there is
less than a full word in the read FIFO, or if a
write cycle starts and there is more than two
bytes in the write FIFO.
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