91C94 Datasheet, PDF (54/120 Pages) SMSC Corporation – ISA/PCMCIA SINGLE CHIP ETHERNET CONTROLLER WITH RAM

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OFFSET
2
NAME
PACKET NUMBER REGISTER
TYPE
READ/WRITE
SYMBOL
PNR
PACKET NUMBER AT TX AREA
0
0
0
0
0
0
0
0
PACKET NUMBER AT TX AREA The value
written into this register determines which
packet number is accessible through the TX
area. Some MMU commands use the number
stored in this register as the packet number
parameter. This register is cleared by a RESET
or a RESET MMU Command.
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OFFSET
NAME
TYPE
SYMBOL
3
ALLOCATION RESULT REGISTER
READ ONLY
ARR
This register is updated upon an ALLOCATE MEMORY MMU command.
FAILED
ALLOCATED PACKET NUMBER
1
0
0
0
0
0
0
0
FAILED A zero indicates a successful allocation
completion. If the allocation fails the bit is set
and only cleared when the pending allocation is
satisfied. Defaults high upon reset and reset
MMU command. For polling purposes, the
ALLOC_INT in the Interrupt Status Register
should be used because it is synchronized to the
read operation. Sequence:
1) Allocate Command
2) Poll ALLOC_INT bit until set
3) Read Allocation Result Register
ALLOCATED PACKET NUMBER Packet
number associated with the last memory
allocation request. The value is only valid if the
FAILED bit is clear.
Note: For software compatibility with future
versions, the value read from the ARR after an
allocation request is intended to be written into
the PNR as is, without masking higher bits
(provided FAILED = 0).
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