91C94 Datasheet, PDF (27/120 Pages) SMSC Corporation – ISA/PCMCIA SINGLE CHIP ETHERNET CONTROLLER WITH RAM

PACKET FORMAT IN BUFFER MEMORY
The packet format in memory is similar for the
TRANSMIT and RECEIVE areas. The first word
is reserved for the status word, the next
word is used to specify the total number of
bytes, and that in turn is followed by the data
area. The data area holds the packet itself, and
its length is determined by the byte count. The
packet memory format is word oriented.
bit15
bit0
RAM
OFFSET
(DECIMAL)
0
STATUS WORD
2
RESERVED
BYTE COUNT (always even)
4
DATA AREA
2046 Max
CONTROL BYTE
LAST DATA BYTE (if odd)
FIGURE 9 – DATA PACKET FORMAT
STATUS WORD
BYTE COUNT
DATA AREA
CONTROL BYTE
TRANSMIT PACKET
RECEIVE PACKET
Written by CSMA upon transmit Written by CSMA upon receive
completion (see Status completion (see RX Frame
Register).
Status Word).
Written by CPU.
Written by CSMA.
Written/modified by CPU.
Written by CSMA.
Written by CPU to control Written by CSMA. Also has
ODD/EVEN data bytes.
ODD/EVEN bit.
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