SI5345_16 Datasheet, PDF (9/60 Pages) Silicon Laboratories – 10-Channel, Any-Frequency, Any-Output Jitter Attenuator/ Clock Multiplier

Si5345/44/42 Rev D Data Sheet
Functional Description
3.7.1 Manual Input Switching (IN0, IN1, IN2, IN3)
Input clock selection can be made manually using the IN_SEL[1:0] pins or through a register. A register bit determines input selection
as pin selectable or register selectable. The IN_SEL pins are selected by default. If there is no clock signal on the selected input, the
device will automatically enter free-run or holdover mode. When the zero delay mode is enabled, IN3 becomes the feedback input
(FB_IN) and is not available for selection as a clock input.
Table 3.1. Manual Input Selection Using IN_SEL[1:0] Pins
IN_SEL[1:0]
0
0
0
1
1
0
1
1
Selected Input
Zero Delay Mode Disabled
Zero Delay Mode Enabled
IN0
IN0
IN1
IN1
IN2
IN2
IN3
Reserved
3.7.2 Automatic Input Selection (IN0, IN1, IN2, IN3)
An automatic input selection state machine is available in addition to the manual switching option. In automatic mode, the selection
criteria is based on input clock qualification, input priority, and the revertive option. Only input clocks that are valid can be selected by
the automatic clock selection state machine. If there are no valid input clocks available the DSPLL will enter the holdover mode. With
revertive switching enabled, the highest priority input with a valid input clock is always selected. If an input with a higher priority be-
comes valid then an automatic switchover to that input will be initiated. With non-revertive switching, the active input will always remain
selected while it is valid. If it becomes invalid an automatic switchover to a valid input with the highest priority will be initiated.
3.7.3 Hitless Input Switching
Hitless switching is a feature that prevents a phase offset from propagating to the output when switching between two clock inputs that
have a fixed phase relationship. A hitless switch can only occur when the two input frequencies are frequency locked meaning that they
have to be exactly at the same frequency, or at a fractional frequency relationship to each other. When hitless switching is enabled, the
DSPLL simply absorbs the phase difference between the two input clocks during a input switch. When disabled, the phase difference
between the two inputs is propagated to the output at a rate determined by the DSPLL Loop Bandwidth. The hitless switching feature
supports clock frequencies down to the minimum input frequency of 8 kHz.
3.7.4 Ramped Input Switching
When switching between two plesiochronous input clocks (i.e., the frequencies are "almost the same" but not quite), ramped input
switching should be enabled to ensure a smooth transition between the two inputs. Ramped input switching avoids frequency transients
and overshoot when switching between frequencies and so is the default switching mode in CBPro. The feature should be turned off
when switching between input clocks that are always frequency locked (i.e., are always the same exact frequency). The same ramp
rate settings are used for both holdover exit and clock switching. For more information on ramped exit from holdover see 3.4.5 Holdover
Mode.
3.7.5 Glitchless Input Switching
The DSPLL has the ability of switching between two input clock frequencies that are up to ±500 ppm apart. The DSPLL will pull-in to the
new frequency using the DSPLL Loop Bandwidth or using the Fastlock Loop Bandwidth if enabled. The loss of lock (LOL) indicator will
assert while the DSPLL is pulling-in to the new clock frequency. There will be no abrupt phase change at the output during the transi-
tion.
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