SI5345_16 Datasheet, PDF (8/60 Pages) Silicon Laboratories – 10-Channel, Any-Frequency, Any-Output Jitter Attenuator/ Clock Multiplier

Si5345/44/42 Rev D Data Sheet
Functional Description
3.6 Digitally Controlled Oscillator (DCO) Mode
The output MultiSynths support a DCO mode where their output frequencies are adjustable in predefined steps defined by frequency
step words (FSW). The frequency adjustments are controlled through the serial interface or by pin control using frequency increment
(FINC) or decrement (FDEC). A FINC will add the frequency step word to the DSPLL output frequency, while a FDEC will decrement it.
Any number of MultiSynths can be updated at once or independently controlled. The DCO mode is available when the DSPLL is operat-
ing in either free-run or locked mode.
25-54MHz
XO
25-54MHz
XO
25-54MHz
XTAL
XA
XB
2xCL
2xCL
OSC
÷ PREF
100
XA
XB
2xCL
OSC
2xCL
÷ PREF
XA
XB
2xCL
OSC
2xCL
÷ PREF
Si5345/44/42
Crystal Resonator
Connection
Si5345/44/42
Differential XO
Connection
Si5345/44/42
Single-Ended XO
Connection
Figure 3.3. Crystal Resonator and External Reference Clock Connection Options
3.7 Inputs (IN0, IN1, IN2, IN3)
There are four inputs that can be used to synchronize the DSPLL. The inputs accept both differential and single-ended clocks. Input
selection can be manual (pin or register controlled) or automatic with user definable priorities.
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