SI5345_16 Datasheet, PDF (29/60 Pages) Silicon Laboratories – 10-Channel, Any-Frequency, Any-Output Jitter Attenuator/ Clock Multiplier

Si5345/44/42 Rev D Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Notes:
1. Output amplitude and common-mode settings are programmable through register settings and can be stored in NVM. Each out-
put driver can be programmed independently. Note that the maximum LVDS single-ended amplitude can be up to 110 mV higher
than the TIA/EIA-644 maximum. Refer to the Si5345/44/42 Family Reference Manual for more suggested output settings. Not all
combinations of voltage amplitude and common mode voltages settings are possible.
OUTx
Vcm
Vcm
Vpp_se
Vpp_se
Vpp_diff = 2*Vpp_se
OUTxb
2. Measured for 156.25 MHz carrier frequency. 100 mVpp sinewave noise added to VDDO = 3.3 V and noise spur amplitude meas-
ured.
3. Measured across two adjacent outputs, both in LVDS mode, with the victim running at 155.52 MHz and the aggressor at 156.25
MHz. Refer to “AN862: Optimizing Si534x Jitter Performance in Next Generation Internet Infrastructure Systems” for guidance on
crosstalk optimization. Note that all active outputs must be terminated when measuring crosstalk.
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