SI5345_16 Datasheet, PDF (19/60 Pages) Silicon Laboratories – 10-Channel, Any-Frequency, Any-Output Jitter Attenuator/ Clock Multiplier

Si5345/44/42 Rev D Data Sheet
Functional Description
3.9.13 Zero Delay Mode
A zero delay mode is available for applications that require fixed and consistent minimum delay between the selected input and outputs.
The zero delay mode is configured by opening the internal feedback loop through software configuration and closing the loop externally
as shown in the figure below.
This helps to cancel out the internal delay introduced by the dividers, the crosspoint, the input, and the output drivers. Any one of the
outputs can be fed back to the FB_IN pins, although using the output driver that achieves the shortest trace length will help to minimize
the input-to-output delay. The OUT9 and FB_IN pins are recommended for the external feedback connection. The FB_IN input pins
must be terminated and ac-coupled when zero delay mode is used. A differential external feedback path connection is necessary for
best performance. Note that the hitless switching feature is not available when zero delay mode is enabled.
IN0
IN0b
IN1
IN1b
IN2
IN2b
IN3/FB_IN
IN3/FB_INb
÷P0
÷P1
÷P2
÷P3
Si5345/44/42
DSPLL
PD LPF
÷M
÷R0
÷N0 t0
÷R1
÷N1 t1
÷R2
÷N2 t2
÷N3 t3
÷R7
÷N4 t4
÷R8
÷R9
VDDO0
OUT0
OUT0b
VDDO1
OUT1
OUT1b
VDDO2
OUT2
OUT2b
VDDO7
OUT7
OUT7b
VDDO8
OUT8
OUT8b
VDDO9
OUT9
OUT9b
External Feedback Path
Figure 3.16. Si5345 Zero Delay Mode Setup
3.9.14 Output Divider (R) Synchronization
All the output R dividers are reset to a known state during the power-up initialization period. This ensures consistent and repeatable
phase alignment across all output drivers. Resetting the device using the RSTb pin or asserting the hard reset bit will have the same
result. Asserting the sync register bit provides another method of realigning the R dividers without resetting the device.
3.10 Power Management
Unused inputs and output drivers can be powered down when unused. Consult the Family Reference Manual and ClockBuilder Pro
configuration utility for details.
3.11 In-Circuit Programming
The Si5345/44/42 is fully configurable using the serial interface (I²C or SPI). At power-up the device downloads its default register val-
ues from internal non-volatile memory (NVM). Application specific default configurations can be written into NVM allowing the device to
generate specific clock frequencies at power-up. Writing default values to NVM is in-circuit programmable with normal operating power
supply voltages applied to its V_DD and V_DDA pins. The NVM is two time writable. Once a new configuration has been written to NVM,
the old configuration is no longer accessible. Refer to the Family Reference Manual for a detailed procedure for writing registers to
NVM.
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