SI5345_16 Datasheet, PDF (14/60 Pages) Silicon Laboratories – 10-Channel, Any-Frequency, Any-Output Jitter Attenuator/ Clock Multiplier

Si5345/44/42 Rev D Data Sheet
Functional Description
An example configuration where LOCK is indicated when there is less than 0.1 ppm frequency difference at the inputs of the phase
detector and LOL is indicated when there’s more than 1 ppm frequency difference is shown in the following figure.
LOL
LOCKED
Clear LOL
Threshold
Set LOL
Threshold
Lock Acquisition
Hysteresis
Lost Lock
0
0.1
1
Phase Detector Frequency Difference (ppm)
Figure 3.11. LOL Set and Clear Thresholds
10,000
Note: In this document, the terms, LVDS and LVPECL, refer to driver formats that are compatible with these signaling standards.
An optional timer is available to delay clearing of the LOL indicator to allow additional time for the DSPLL to completely lock to the input
clock. The timer is also useful to prevent the LOL indicator from toggling or chattering as the DSPLL completes lock acquisition. The
configurable delay value depends on frequency configuration and loop bandwidth of the DSPLL and is automatically calculated using
the ClockBuilder Pro utility.
3.8.5 Interrupt Pin (INTRb)
An interrupt pin (INTRb) indicates a change in state of the status indicators (LOS, OOF, LOL, HOLD). Any of the status indicators are
maskable to prevent assertion of the interrupt pin. The state of the INTRb pin is reset by clearing the status register that caused the
interrupt.
3.9 Outputs
Each driver has a configurable voltage swing and common mode voltage covering a wide variety of differential signal formats. In addi-
tion to supporting differential signals, any of the outputs can be configured as single-ended LVCMOS (3.3 V, 2.5 V, or 1.8 V) providing
up to 20 single-ended outputs, or any combination of differential and single-ended outputs.
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