SI5345_16 Datasheet, PDF (13/60 Pages) Silicon Laboratories – 10-Channel, Any-Frequency, Any-Output Jitter Attenuator/ Clock Multiplier

Si5345/44/42 Rev D Data Sheet
Functional Description
3.8.3.1 Precision OOF Monitor
The precision OOF monitor circuit measures the frequency of all input clocks to within ±1/16 ppm accuracy with respect to the selected
OOF frequency reference. A valid input clock frequency is one that remains within the OOF frequency range which is register configura-
ble up to ±500 ppm in steps of 1/16 ppm. A configurable amount of hysteresis is also available to prevent the OOF status from toggling
at the failure boundary. An example is shown in the figure below. In this case, the OOF monitor is configured with a valid frequency
range of ±6 ppm and with 2 ppm of hysteresis. An option to use one of the input pins (IN0–IN3) as the 0 ppm OOF reference instead of
the XA/XB pins is available. This option is register configurable.
OOF Declared
OOF Cleared
Hysteresis
-6 ppm
(Set)
-4 ppm
(Clear)
0 ppm
OOF Reference
fIN
Hysteresis
+4 ppm
(Clear)
+6 ppm
(Set)
Figure 3.9. Example of Precise OOF Monitor Assertion and Deassertion Triggers
3.8.3.2 Fast OOF Monitor
Because the precision OOF monitor needs to provide 1/16 ppm of frequency measurement accuracy, it must measure the monitored
input clock frequencies over a relatively long period of time. This may be too slow to detect an input clock that is quickly ramping in
frequency. An additional level of OOF monitoring called the Fast OOF monitor runs in parallel with the precision OOF monitors to quick-
ly detect a ramping input frequency. The Fast OOF monitor asserts OOF on an input clock frequency that has changed by greater than
±4000 ppm.
3.8.4 LOL Detection
The Loss Of Lock (LOL) monitor asserts a LOL register bit when the DSPLL has lost synchronization with its selected input clock.
There is also a dedicated loss of lock pin that reflects the loss of lock condition. The LOL monitor functions by measuring the frequency
difference between the input and feedback clocks at the phase detector. There are two LOL frequency monitors, one that sets the LOL
indicator (LOL Set) and another that clears the indicator (LOL Clear). An optional timer is available to delay clearing of the LOL indicator
to allow additional time for the DSPLL to completely lock to the input clock. The timer is also useful to prevent the LOL indicator from
toggling or chattering as the DSPLL completes lock acquisition. A block diagram of the LOL monitor is shown in the figure below. The
live LOL register always displays the current LOL state and a sticky register always stays asserted until cleared. The LOL pin reflects
the current state of the LOL monitor.
LOL Monitor
LOL
Clear
LOL
Set
Timer
DSPLL
fIN
PD LPF
Feedback
Clock
÷M
LOLOLS
Live
Sticky
LOLb
Si5345/44/42
Figure 3.10. LOL Status Indicators
The LOL frequency monitors have an adjustable sensitivity which is register configurable from 0.1 ppm to 10,000 ppm. Having two sep-
arate frequency monitors allows for hysteresis to help prevent chattering of LOL status.
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