SI5345_16 Datasheet, PDF (7/60 Pages) Silicon Laboratories – 10-Channel, Any-Frequency, Any-Output Jitter Attenuator/ Clock Multiplier

Si5345/44/42 Rev D Data Sheet
Functional Description
3.4.5 Holdover Mode
The DSPLL will automatically enter holdover mode when the selected input clock becomes invalid and no other valid input clocks are
available for selection. The DSPLL uses an averaged input clock frequency as its final holdover frequency to minimize the disturbance
of the output clock phase and frequency when an input clock suddenly fails. The holdover circuit for the DSPLL stores up to 120 sec-
onds of historical frequency data while locked to a valid clock input. The final averaged holdover frequency value is calculated from a
programmable window within the stored historical frequency data. Both the window size and the delay are programmable as shown in
the figure below. The window size determines the amount of holdover frequency averaging. The delay value allows ignoring frequency
data that may be corrupt just before the input clock failure.
Historical Frequency Data Collected
Clock Failure and Entry
into Holdover
time
Programmable historical data window used to
Programmable delay
120s
determine the final holdover value
30ms, 60ms, 1s,10s, 30s, 60s
0s
1s,10s, 30s, 60s
Figure 3.2. Programmable Holdover Window
When entering holdover, the DSPLL will pull its output clock frequency to the calculated averaged holdover frequency. While in hold-
over, the output frequency drift is entirely dependent on the external crystal or external reference clock connected to the XA/XB pins. If
the clock input becomes valid, the DSPLL will automatically exit the holdover mode and re-acquire lock to the new input clock. This
process involves pulling the output clock frequency to achieve frequency and phase lock with the input clock. This pull-in process is
glitchless and its rate is controlled by the DSPLL or the Fastlock bandwidth.
The DSPLL output frequency when exiting holdover can be ramped (recommend). Just before the exit is initiated, the difference be-
tween the current holdover frequency and the new desired frequency is measured. Using the calculated difference and a user-selecta-
ble ramp rate, the output is linearly ramped to the new frequency. The ramp rate can be 0.2 ppm/s, 40,000 ppm/s, or any of about 40
values in between. The DSPLL loop BW does not limit or affect ramp rate selections (and vice versa). CBPro defaults to ramped exit
from holdover. The same ramp rate settings are used for both exit from holdover and ramped input switching. For more information on
ramped input switching, see 3.7.4 Ramped Input Switching.
Note: If ramped holdover exit is not selected, the holdover exit is governed either by (1) the DSPLL loop BW or (2) a user-selectable
holdover exit BW.
3.5 External Reference (XA/XB)
An external crystal (XTAL) is used in combination with the internal oscillator (OSC) to produce an ultra low jitter reference clock for the
DSPLL and for providing a stable reference for the free-run and holdover modes. A simplified diagram is shown in Figure 3.3 Crystal
Resonator and External Reference Clock Connection Options on page 7. The device includes internal XTAL loading capacitors
which eliminates the need for external capacitors and also has the benefit of reduced noise coupling from external sources. Refer to
Table 5.12 Crystal Specifications on page 36 for crystal specifications. A crystal in the range of 48 MHz to 54 MHz is recommended
for best jitter performance. Frequency offsets due to CL mismatch can be adjusted using the frequency adjustment feature which allows
frequency adjustments of ±200 ppm. The Si5345/44/42 Family Reference Manual provides additional information on PCB layout recom-
mendations for the crystal to ensure optimum jitter performance.
To achieve optimal jitter performance and minimize BOM cost, a crystal is recommended on the XA/XB reference input. For SyncE line
card PLL applications (e.g. loop bandwidth set to 0.1 Hz), a TCXO is required on the XA/XB reference to minimize wander and to pro-
vide a stable holdover reference. See the Si5345/44/42 Family Reference Manual for more information. Selection between the external
XTAL or REFCLK is controlled by register configuration. The internal crystal loading capacitors (CL) are disabled in the REFCLK mode.
Refer to Table 5.3 Input Clock Specifications on page 25 for REFCLK requirements when using this mode. A PREF divider is availa-
ble to accommodate external clock frequencies higher than 54 MHz. Frequencies in the range of 48 MHz to 54 MHz will achieve the
best output jitter performance.
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