SI5345_16 Datasheet, PDF (27/60 Pages) Silicon Laboratories – 10-Channel, Any-Frequency, Any-Output Jitter Attenuator/ Clock Multiplier

Si5345/44/42 Rev D Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Input Duty Cycle
DC
40
—
60
%
Note:
1. Voltage swing is specified as single-ended mVpp.
OUTx
Vcm
OUTxb
Vcm
Vpp_se
Vpp_se
Vpp_diff = 2*Vpp_se
2. Imposed for jitter performance.
3. Rise and fall times can be estimated using the following simplified equation: tr/tf_80-20 = ((0.8 – 0.2) x V_{IN_Vpp_se}) / SR. Pulsed
CMOS mode is intended primarily for single-ended LVCMOS input clocks < 1 MHz that must be dc-coupled because they have a
duty cycle significantly less than 50%. A typical application example is a low-frequency video frame sync pulse. Since the input
thresholds (V_IL, V_IH) of this buffer are non-standard (0.4 and 0.8 V, respectively) refer to the input attenuator circuit for dc-coupled
pulsed LVCMOS in the Family Reference Manual. Otherwise, for standard LVCMOS input clocks, use the Standard Differential or
Single-Ended ac-coupled input mode.
Table 5.4. Control Input Pin Specifications
V_DD = 1.8 V ±5%, V_DDA = 3.3 V ±5%, V_DDS = 3.3 V ±5%, 1.8 V ±5%, T_A = –40 to 85 °C
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Si5345 Control Input Pins (I2C_SEL, IN_SEL[1:0], RSTb, OEb, A1, SCLK, A0/CSb, FINC, FDEC, SDA/SDIO)
V_IL
Input Voltage
V_IH
—
—
0.3 ×
V_DDIO1
V
0.7 ×
V_DDIO1
—
—
V
Input Capacitance
C_IN
—
2
—
pF
Input Resistance
R_IN
—
20
—
kΩ
Minimum Pulse Width
PW
RSTb, FINC and FDEC
100
—
—
ns
Update Rate
T_UR
FINC and FDEC
1
—
—
µs
Si5344/42 Control Input Pins (I2C_SEL, IN_SEL[1:0], RSTb, OEb, A1, SCLK, A0/CSb, SDA/SDIO)
V_IL
Input Voltage
V_IH
—
—
0.3 ×
V_DDIO1
V
0.7 ×
V_DDIO1
—
—
V
Input Capacitance
C_IN
—
2
—
pF
Input Resistance
R_IN
—
20
—
kΩ
Minimum Pulse Width
PW
RSTb
100
—
—
ns
Note:
1. V_DDIO is determined by the IO_VDD_SEL bit. It is selectable as V_DDA or V_DD. See the Family Reference Manual for more details
on the proper register settings.
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