SI5345_16 Datasheet, PDF(33/60 Page) Silicon Laboratories – 10-Channel, Any-Frequency, Any-Output Jitter Attenuator/ Clock Multiplier

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SI5345_16 Datasheet, PDF (33/60 Pages) Silicon Laboratories – 10-Channel, Any-Frequency, Any-Output Jitter Attenuator/ Clock Multiplier

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Si5345/44/42 Rev D Data Sheet

Electrical Specifications

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Measured between a

common 2 MHz input and

2 MHz output with differ-

ent MultiSynths on the

1.8

same unit.

DSPLL BW = 4 kHz

tIODELAY

Measured between a

2.0

common 2 MHz input and

2 MHz output with differ-

Input-to-Output Delay Variation

ent MultiSynths between

units.

DSPLL bandwidth = 4

kHz

Delay between reference

and feedback input with

tZDELAY

both clocks at 10 MHz

and same slew rate. Ref

110

clock rise time must be

<200 ps.

RMS Phase Jitter4

Integer Mode

145

fs rms

12 kHz to 20 MHz

JGEN

Fractional Mode

120

170

fs rms

12 kHz to 20 MHz

Note:

1. Actual loop bandwidth might be lower; please refer to CBPro for actual value for your frequency plan.

2. Lock Time can vary significantly depending on several parameters, such as bandwidths, LOL tresholds, etc. For this case, lock

time was measured with nominal and fastlock bandwidths set to 100 Hz, LOL set/clear thresholds of 6/0.6 ppm respectively, us-

ing IN0 as clock reference by removing the reference and enabling it again, then measuring the delta time between the first rising

edge of the clock reference and the LOL indicator deassertion.

3. Measured as time from valid VDD/VDDA rails (90% of their value) to when the serial interface is ready to respond to commands.

4. Jitter generation test conditions: fIN = 19.44 MHz, fOUT = 156.25 MHz LVPECL, loop bandwidth = 100 Hz, FXTAL = 48 MHz.

Table 5.9. I2C Timing Specifications (SCL,SDA)

Parameter

Symbol

SCL Clock Frequency

SMBus Timeout

Hold time (Repeated)

START condition

Low Period of the SCL Clock

HIGH Period of the SCL

Clock

Setup Time for a Repeated

START Condition

fSCL

tHD:STA

tLOW

tHIGH

tSU:STA

Test Condition

When Timeout is

Enabled

Standard Mode

100 kbps

Min

Max

100

4.0

4.7

4.0

4.7

Fast Mode

400 kbps

Min

Max

400

0.6

1.3

0.6

Unit

kHz

Âµs

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