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SI5345_16 Datasheet, PDF (17/60 Pages) Silicon Laboratories – 10-Channel, Any-Frequency, Any-Output Jitter Attenuator/ Clock Multiplier
Si5345/44/42 Rev D Data Sheet
Functional Description
3.9.6 LVCMOS Output Impedance Selection
Each LVCMOS driver has a configurable output impedance to accommodate different trace impedances. A source termination resistor
is recommended to help match the selected output impedance to the trace impedance, where Rs = Transmission line impedance – ZO.
There are three programmable output impedance selections (CMOS1, CMOS2, CMOS3) for each VDDO option as shown in the follow-
ing table.
Table 3.2. Typical Output Impedance (ZS)
VDDO
3.3 V
2.5 V
1.8 V
OUTx_CMOS_DRV = 1
38 Ω
43 Ω
—
CMOS Drive Selections
OUTx_CMOS_DRV = 2
30 Ω
35 Ω
46 Ω
OUTx_CMOS_DRV = 3
22 Ω
24 Ω
31 Ω
3.9.7 LVCMOS Output Signal Swing
The signal swing (VOL/VOH) of the LVCMOS output drivers is set by the voltage on the VDDO pins. Each output driver has its own
VDDO pin allowing a unique output voltage swing for each of the LVCMOS drivers.
3.9.8 LVCMOS Output Polarity
When a driver is configured as an LVCMOS output, it generates a clock signal on both pins (OUTx and OUTxb). By default, the clock
on the OUTx pin is generated with the same polarity (in phase) as the clock on the OUTxb pin. The polarity of these clocks is configura-
ble, enabling complementary clock generation and/or inverted polarity with respect to other output drivers.
3.9.9 Output Enable/Disable
The OEb pin provides a convenient method of disabling or enabling the output drivers. When the OEb pin is held high, all outputs are
disabled. When held low, the outputs are enabled. Outputs in the enabled state can be individually disabled through register control.
3.9.10 Output Driver State When Disabled
The disabled state of an output driver is configurable as disable low or disable high.
3.9.11 Synchronous Output Disable Feature
The output drivers provide a selectable synchronous disable feature. Output drivers with this feature turned on will wait until a clock
period has completed before the driver is disabled. This prevents unwanted runt pulses from occurring when disabling an output. When
this feature is turned off, the output clock will disable immediately without waiting for the period to complete.
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