SI5345_16 Datasheet, PDF (26/60 Pages) Silicon Laboratories – 10-Channel, Any-Frequency, Any-Output Jitter Attenuator/ Clock Multiplier

Si5345/44/42 Rev D Data Sheet
Electrical Specifications
Table 5.3. Input Clock Specifications
V_DD = 1.8 V ±5%, V_DDA = 3.3 V ±5%, T_A = –40 to 85 °C
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Standard Input Buffer with Differential or Single-Ended - AC Coupled (IN0/IN0, IN1/IN1, IN2/IN2, IN3/IN3, FB_IN/FB_IN)
Differential
0.008
—
750
MHz
Input Frequency Range
f_IN
All Single-ended signals
0.008
—
250
MHz
(including LVCMOS)
Differential AC-coupled
100
f_IN < 250 MHz
—
1800
mVpp_se
Voltage Swing¹
Differential AC-coupled
V_IN
225
250 MHz < f_IN < 750 MHz
—
1800
mVpp_se
Single-ended AC-coupled
100
f_IN < 250 MHz
—
3600
mVpp_se
Slew Rate^{2, 3}
SR
400
—
—
V/µs
Duty Cycle
DC
40
—
60
%
Input Capacitance
C_IN
—
0.3
—
pF
Input Resistance
R_IN
—
16
—
kΩ
Pulsed CMOS Input Buffer—DC Coupled (IN0, IN1, IN2, IN4)³
Input Frequency
f_{IN_PULSED_CM}
OS
0.008
—
250
MHz
V_IL
Input Voltage
V_IH
–0.2
—
0.4
V
0.8
—
—
V
Slew Rate^{2, 3}
SR
400
—
—
V/µs
Duty Cycle
DC
40
—
60
%
Minimum Pulse Width
PW
Pulse Input
1.6
—
—
ns
Input Resistance
R_IN
—
8
—
kΩ
REFCLK (Applied to XA/XB)
Full operating range. Jit-
ter performance may be
24.97
—
54.06
MHz
reduced.
REFCLK Frequency
f_{IN_REF}
Range for best jitter.
48
—
54
MHz
TCXO frequency for
SyncE applications. Jitter
performance may be re-
—
40
—
MHz
duced.
Input Single-ended Voltage
Swing
V_{IN_SE}
365
—
2000
mVpp_se
Input Differential Voltage Swing V_{IN_DIFF}
365
2500
mVpp_diff
Slew Rate^{2, 3}
SR
400
—
—
V/µs
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