SI5345_16 Datasheet, PDF (5/60 Pages) Silicon Laboratories – 10-Channel, Any-Frequency, Any-Output Jitter Attenuator/ Clock Multiplier

Si5345/44/42 Rev D Data Sheet
Functional Description
3. Functional Description
The Si5345’s internal DSPLL provides jitter attenuation and any-frequency multiplication of the selected input frequency. Fractional in-
put dividers (P) allow the DSPLL to perform hitless switching between input clocks (INx) that are fractionally related. Input switching is
controlled manually or automatically using an internal state machine. The oscillator circuit (OSC) provides a frequency reference which
determines output frequency stability and accuracy while the device is in free-run or holdover mode. The high-performance MultiSynth
dividers (N) generate integer or fractionally related output frequencies for the output stage. A crosspoint switch connects any of the
MultiSynth generated frequencies to any of the outputs. Additional integer division (R) determines the final output frequency.
3.1 Frequency Configuration
The frequency configuration of the DSPLL is programmable through the serial interface and can also be stored in non-volatile memory.
The combination of fractional input dividers (P_n/P_d), fractional frequency multiplication (M_n/M_d), fractional output MultiSynth division
(N_n/N_d), and integer output division (R_n) allows the generation of virtually any output frequency on any of the outputs. All divider values
for a specific frequency plan are easily determined using the ClockBuilder Pro utility.
3.2 DSPLL Loop Bandwidth
The DSPLL loop bandwidth determines the amount of input clock jitter attenuation. Register configurable DSPLL loop bandwidth set-
tings in the range of 0.1 Hz to 4 kHz are available for selection. Since the loop bandwidth is controlled digitally, the DSPLL will always
remain stable with less than 0.1 dB of peaking regardless of the loop bandwidth selection.
3.3 Fastlock Feature
Selecting a low DSPLL loop bandwidth (e.g. 0.1 Hz) will generally lengthen the lock acquisition time. The fastlock feature allows setting
a temporary Fastlock Loop Bandwidth that is used during the lock acquisition process. Higher fastlock loop bandwidth settings will ena-
ble the DSPLLs to lock faster. Fastlock Loop Bandwidth settings of in the range of 100 Hz to 4 kHz are available for selection. The
DSPLL will revert to its normal loop bandwidth once lock acquisition has completed.
3.4 Modes of Operation
Once initialization is complete the DSPLL operates in one of four modes: Free-run Mode, Lock Acquisition Mode, Locked Mode, or
Holdover Mode. A state diagram showing the modes of operation is shown in Figure 3.1 Modes of Operation on page 5. The follow-
ing sections describe each of these modes in greater detail.
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