SI5345_16 Datasheet, PDF (23/60 Pages) Silicon Laboratories – 10-Channel, Any-Frequency, Any-Output Jitter Attenuator/ Clock Multiplier

16-Bit Address
8-bit Page Address
8-bit Register Address Range
01
02–37
0C
17
22
03
2D
38
39–58
59–62
FE
04
87
0E–14
15–1F
2A
2B
05
2C–35
36
38–39
3F
06–08
00–FF
09
01
1C
43
49
10–FF
00–FF
Si5345/44/42 Rev D Data Sheet
Register Map
Content
Set Page Address
MultiSynth Divider (N0–N4) Settings
MultiSynth Divider (N0) Update Bit
MultiSynth Divider (N1) Update Bit
MultiSynth Divider (N2) Update Bit
MultiSynth Divider (N3) Update Bit
MultiSynth Divider (N4) Update Bit
FINC/FDEC Settings N0–N4
Output Delay (Δt) Settings
Device Ready Status
Zero Delay Mode Set Up
Fast Lock Loop Bandwidth
Feedback Divider (M) Settings
Input Select Control
Fast Lock Control
Holdover Settings
Input Clock Switching Mode Select
Input Priority Settings
Holdover History Valid Data
Reserved
Set Page Address
Zero Delay Mode Settings
Control I/O Voltage Select
Input Settings
Reserved
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