SI5345_16 Datasheet, PDF (6/60 Pages) Silicon Laboratories – 10-Channel, Any-Frequency, Any-Output Jitter Attenuator/ Clock Multiplier

Si5345/44/42 Rev D Data Sheet
Functional Description
3.4.1 Initialization and Reset
Once power is applied, the device begins an initialization period where it downloads default register values and configuration data from
NVM and performs other initialization tasks. Communicating with the device through the serial interface is possible once this initializa-
tion period is complete. No clocks will be generated until the initialization is complete. There are two types of resets available. A hard
reset is functionally similar to a device power-up. All registers will be restored to the values stored in NVM, and all circuits including the
serial interface will be restored to their initial state. A hard reset is initiated using the RSTb pin or by asserting the hard reset register bit.
A soft reset bypasses the NVM download. It is simply used to initiate register configuration changes.
No valid input
clocks available
for selection
Power-Up
Reset and
Initialization
No valid
input clocks
selected
An input is
qualified and
available for
selection
Holdover
Mode
Free-run
Valid input clock
selected
Lock Acquisition
(Fast Lock)
Phase lock on
selected input
clock is achieved
Input Clock
Switch
Yes
No
Holdover
History
Valid?
Locked
Mode
Selected input
clock fails
Yes _{Other Valid}
Clock Inputs
No ^Available?
Figure 3.1. Modes of Operation
3.4.2 Freerun Mode
The DSPLL will automatically enter freerun mode once power is applied to the device and initialization is complete. The frequency ac-
curacy of the generated output clocks in freerun mode is entirely dependent on the frequency accuracy of the external crystal or refer-
ence clock on the XA/XB pins. For example, if the crystal frequency is ±100 ppm, then all the output clocks will be generated at their
configured frequency ±100 ppm in freerun mode. Any drift of the crystal frequency will be tracked at the output clock frequencies. A
TCXO or OCXO is recommended for applications that need better frequency accuracy and stability while in freerun or holdover modes.
3.4.3 Lock Acquisition Mode
The device monitors all inputs for a valid clock. If at least one valid clock is available for synchronization, the DSPLL will automatically
start the lock acquisition process. If the fast lock feature is enabled, the DSPLL will acquire lock using the Fastlock Loop Bandwidth
setting and then transition to the DSPLL Loop Bandwidth setting when lock acquisition is complete. During lock acquisition the outputs
will generate a clock that follows the VCO frequency change as it pulls in to the input clock frequency.
3.4.4 Locked Mode
Once locked, the DSPLL will generate output clocks that are both frequency and phase locked to their selected input clocks. At this
point, any XTAL frequency drift will not affect the output frequency. A loss of lock pin (LOL) and status bit indicate when lock is ach-
ieved. See 3.8.4 LOL Detection for more details on the operation of the loss-of-lock circuit.
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