SI5345_16 Datasheet, PDF (16/60 Pages) Silicon Laboratories – 10-Channel, Any-Frequency, Any-Output Jitter Attenuator/ Clock Multiplier

Si5345/44/42 Rev D Data Sheet
Functional Description
3.9.3 Differential Output Terminations
The differential output drivers support both ac-coupled and dc-coupled terminations as shown in the figure below.
Note: In this document, the terms, LVDS and LVPECL, refer to driver formats that are compatible with these signaling standards.
DC Coupled LVDS/LVPECL
VDDO = 3.3V, 2.5V, 1.8V
Si5345/44/42
OUTx
OUTxb
50
100
50
AC Coupled LVDS/LVPECL
VDDO = 3.3V, 2.5V, 1.8V
OUTx
50
OUTxb
100
50
Si5345/44/42
Internally
self-biased
VDDO = 3.3V, 2.5V
AC Coupled LVPECL
VDD – 1.3V
50
50
OUTx
50
OUTxb
50
Si5345/44/42
Figure 3.13. Supported Differential Output Terminations
3.9.4 LVCMOS Output Terminations
LVCMOS outputs are dc-coupled, as shown in the following figure.
DC Coupled LVCMOS
VDDO = 3.3V, 2.5V, 1.8V
OUTx
Rs
OUTxb
3.3V, 2.5V, 1.8V
LVCMOS
50
Si5345/44/42
50
Rs
Figure 3.14. LVCMOS Output Terminations
3.9.5 Programmable Common Mode Voltage For Differential Outputs
The common mode voltage (V_CM) for the differential modes are programmable so that LVDS specifications can be met and for the best
signal integrity with different supply voltages. When dc coupling the output driver, it is essential that the receiver have a relatively high
common mode impedance so that the common mode current from the output driver is very small.
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