SI5345_16 Datasheet, PDF (28/60 Pages) Silicon Laboratories – 10-Channel, Any-Frequency, Any-Output Jitter Attenuator/ Clock Multiplier

Si5345/44/42 Rev D Data Sheet
Electrical Specifications
Table 5.5. Differential Clock Output Specifications
V_DD = 1.8 V ±5%, V_DDA = 3.3 V ±5%, V_DDO = 1.8 V ±5%, 2.5 V ±5%, or 3.3 V ±5%, T_A = –40 to 85 °C
Parameter
Si5342/44/45
Output Frequency
Duty Cycle
Output-Output Skew
Using Same MultiSynth
Output-Output Skew
Between MultiSynths
OUT-OUTb Skew
Output Voltage Swing¹
Common Mode Voltage^{1, 2}
(100 Ω load line-to-line)
Rise and Fall Times
(20% to 80%)
Differential Output Impedance
Power Supply Noise Rejec-
tion²
Output-output Crosstalk³
Symbol
Test Condition
f_OUT
MultiSynth not used
DC
T_SKS
T_SKD
TSK_OUT
VOUT
VCM
MultiSynth used
f_OUT < 400 MHz
400 MHz < f_OUT < 1028
MHz
Outputs on same
MultiSynth
(Measured at 712.5 MHz)
Outputs from different
MultiSynths
(Measured at 712.5 MHz)
Measured from the positive
to negative output pins
V_DDO = 3.3 V,
2.5 V, 1.8 V
LVDS
V_DDO = 3.3 V,
2.5 V
LVPECL
V_DDO = 3.3 V
LVDS
LVPECL
V_DDO = 2.5 V
LVPECL
LVDS
V_DDO = 1.8 V sub-LVDS
tR/tF
ZO
PSRR
XTALK
10 kHz sinusoidal noise
100 kHz sinusoidal noise
500 kHz sinusoidal noise
1 MHz sinusoidal noise
Si5345
Si5342/44
Min
0.0001
733.33
825
0.0001
48
45
—
—
—
350
640
1.10
1.90
1.1
0.8
—
—
—
—
—
—
—
—
Typ
—
—
—
—
—
—
—
—
0
430
750
1.2
2.0
1.2
0.9
100
100
–101
–96
–99
–97
–72
–88
Max
720
800.00
1028
720
52
55
65
Unit
MHz
MHz
MHz
MHz
%
%
ps
90
ps
50
ps
510
mVpp_se
900
mVpp_se
1.3
V
2.1
V
1.3
V
1.0
V
150
ps
—
Ω
—
dBc
—
dBc
—
dBc
—
dBc
—
dBc
—
dBc
silabs.com | Smart. Connected. Energy-friendly.
Rev. 1.0 | 27