SI5345_16 Datasheet, PDF (46/60 Pages) Silicon Laboratories – 10-Channel, Any-Frequency, Any-Output Jitter Attenuator/ Clock Multiplier

Si5345/44/42 Rev D Data Sheet
Pin Descriptions
Table 9.1. Si5345/44/42 Pin Descriptions
Pin Name
Inputs
XA
XB
X1
Si5345
Pin Number
Si5344
Si5342
8
5
5
9
6
6
7
4
4
X2
10
7
7
IN0
63
43
43
IN0b
64
44
44
IN1
1
1
1
IN1b
2
2
2
IN2
14
10
10
IN2b
15
11
11
IN3/FB_IN
61
41
41
IN3b/FB_INb
62
42
42
Pin Type¹
Function
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Crystal Input. Input pins for external crystal (XTAL). Alternatively
these pins can be driven with an external reference clock
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(REFCLK). An internal register bit selects XTAL or REFCLK
mode. Default is XTAL mode.
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XTAL Shield. Connect these pins directly to the XTAL ground
pins. X1, X2 and the XTAL ground pins should be separated from
the PCB ground plane. Refer to the Si5345/44/42 Family Refer-
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ence Manual for layout guidelines. These pins should be left dis-
connected when connecting XA/XB pins to an external reference
clock (REFCLK).
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I
Clock Inputs. These pins accept an input clock for synchronizing
the device. They support both differential and single-ended clock
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signals. Refer to 3.7.6 Input Configuration and Terminations for
input termination options. These pins are high-impedance and
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must be terminated externally. The negative side of the differen-
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tial input must be grounded through a capacitor when accepting a
single-ended clock.
I
I
Clock Input 3/External Feedback Input. By default these pins
are used as the fourth clock input (IN3/IN3b). They can also be
used as the external feedback input (FB_IN/FB_INb) for the op-
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tional zero delay mode. See 3.9.13 Zero Delay Mode for details
on the optional zero delay mode.
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