SI5345_16 Datasheet, PDF (10/60 Pages) Silicon Laboratories – 10-Channel, Any-Frequency, Any-Output Jitter Attenuator/ Clock Multiplier

Si5345/44/42 Rev D Data Sheet
Functional Description
3.7.6 Input Configuration and Terminations
Each of the inputs can be configured as differential or single-ended LVCMOS. The recommended input termination schemes are shown
in Figure 14. Differential signals must be ac-coupled, while single-ended LVCMOS signals can be ac or dc-coupled. Unused inputs can
be disabled and left unconnected when not in use.
Standard AC Coupled Differential LVDS
50
3.3V, 2.5V
LVDS or
50
CML
INx
100
INxb
Si5345/44/42
Standard
Pulsed CMOS
Standard AC Coupled Differential LVPECL
50
3.3V, 2.5V
50
LVPECL
INx
100
INxb
Si5345/44/42
Standard
Pulsed CMOS
Standard AC Coupled Single Ended
50
3.3V, 2.5V, 1.8V
LVCMOS
INx
INxb
Si5345/44/42
Standard
Pulsed CMOS
Pulsed CMOS DC Coupled Single Ended
R1
50
3.3V, 2.5V, 1.8V
R2
LVCMOS
VDD
1.8 V
2.5 V
3.3 V
R1 (Ohm) R2 (Ohm)
324
665
511
475
634
365
INx
INxb
Si5345/44/42
Standard
Pulsed CMOS
Figure 3.4. Termination of Differential and LVCMOS Input Signals
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