SI5345_16 Datasheet, PDF (18/60 Pages) Silicon Laboratories – 10-Channel, Any-Frequency, Any-Output Jitter Attenuator/ Clock Multiplier

Si5345/44/42 Rev D Data Sheet
Functional Description
3.9.12 Output Skew Control (Δt₀ – Δt₄)
The Si5345/44/42 uses independent MultiSynth dividers (N₀ – N₄) to generate up to five unique frequencies to its ten outputs through a
crosspoint switch. By default, all clocks are phase-aligned. A delay path (Δt₀ – Δt₄) associated with each of these dividers is available
for applications that need a specific output skew configuration. This is useful for PCB trace length mismatch compensation. The resolu-
tion of the phase adjustment is approximately 0.28 ps per step, definable in a range of ±9.14 ns. Phase adjustments are register-config-
urable. An example of generating two frequencies with unique configurable path delays is shown in the following figure.
÷N0 t0
÷N1 t1
÷N2 t2
÷N3 t3
÷N4 t4
÷R0
÷R1
÷R2
÷R3
÷R4
÷R5
÷R6
÷R7
÷R8
÷R9
VDDO0
OUT0
OUT0b
VDDO1
OUT1
OUT1b
VDDO2
OUT2
OUT2b
VDDO3
OUT3
OUT3b
VDDO4
OUT4
OUT4b
VDDO5
OUT5
OUT5b
VDDO6
OUT6
OUT6b
VDDO7
OUT7
OUT7b
VDDO8
OUT8
OUT8b
VDDO9
OUT9
OUT9b
Figure 3.15. Example of Independently-Configurable Path Delays
All phase delay values are restored to their default values after power-up, hard reset, or a reset using the RSTb pin. Phase delay de-
fault values can be written to NVM, allowing a custom phase offset configuration at power-up or after power-on reset, or after a hard-
ware reset using the RSTb pin.
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