SI5317 Datasheet, PDF (9/50 Pages) Silicon Laboratories – Pin-Controlled 1_710 MHz Jitter Cleaning Clock

1.1. Three-Level (3L) Input Pins (No External Resistors)
Si5317 ^VDD
I_imm
75 k
Si5317
External Driver
75 k
Figure 3. Three Level Input Pins
1.2. Three-Level Input Pins (with External Resistors)
V_DD
I_imm ^{18 k}
V_DD
Si5317
75 k
External Driver
18 k
75 k
One of eight resistors from a Panasonic EXB-D10C183J
(or similar) resistor pack
Figure 4. Three-Level Input Pins
Table 3. Three-Level Input Pins^1,2,3,4
Parameter
Symbol
Min
Max
Input Low Current
Iill
–30 µA
—
Input Mid Current
Iimm
–11 µA
–11 µA
Input High Current
Iihh
—
–30 µA
Notes:
1. The current parameters are the amount of leakage that the 3L inputs can tolerate from an external driver. In most
designs, an external resistor voltage divider is recommended.
2. Resistor packs are only needed if the leakage current of the external driver exceeds the listed currents.
Any resistor pack may be used (e.g. Panasonic EXB-D10C183J). PCB layout is not critical.
3. If a pin is tied to ground or V_DD, no resistors are needed.
4. If a pin is left open (no connect), no resistors are needed.
Preliminary Rev. 0.15
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