SI5317 Datasheet, PDF (10/50 Pages) Silicon Laboratories – Pin-Controlled 1_710 MHz Jitter Cleaning Clock

Si5317
Table 4. AC Characteristics
(V_DD = 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%, T_A = –40 to 85 ºC)
Parameter
Input Frequency
CKIN Input Pins
Input Duty Cycle (Minimum Pulse
Width)
Input Capacitance
Input Rise/Fall Time
CKOUT Output Pins
Output Frequency (Output not
configured for CMOS or disable)
Maximum Output Frequency in
CMOS Format
Single-ended Output Rise/Fall
(20–80%)
Differential Output Rise/Fall Time
Output Duty Cycle Differential
Uncertainty
Symbol
Test Condition
Min
CKN_F
1
Whichever is smaller
40
CKN_DC
2
CKN_CIN
—
CKN_TRF
20–80%
—
See Figure 2
CK_OF
1
CKO_FMC
1
CMOS Output
—
CKO_TRF
V_DD = 1.62
Cload = 5 pF
CMOS Output
—
V_DD = 2.97
Cload = 5 pF
CKO_TRF 20 to 80 %, f_OUT = 622.08 —
CKO_DC
100  Load
—
Line to Line
Measured at 50% Point
(not for CMOS)
LVCMOS Pins
Input Capacitance
C_IN
—
Typ Max Units
—
710 MHz
—
60
%
—
—
ns
—
3
pF
—
11
ns
—
710 MHz
— 212.5 MHz
—
8
ns
—
2
ns
230 350 ps
—
±40 ps
—
3
pF
10
Preliminary Rev. 0.15