SI5317 Datasheet, PDF (4/50 Pages) Silicon Laboratories – Pin-Controlled 1_710 MHz Jitter Cleaning Clock

Si5317
1. Electrical Specifications
Table 1. Recommended Operating Conditions
(V_DD = 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%, T_A = –40 to 85 ºC)
Parameter
Temperature Range
Supply Voltage
Symbol
T_A
V_DD
Test Condition
3.3 V nominal
2.5 V nominal
1.8 V nominal
Min
Typ
Max Unit
–40
25
85
ºC
2.97
3.3
3.63
V
2.25
2.5
2.75
V
1.71
1.8
1.89
V
Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.
Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise noted.
Table 2. DC Characteristics
(V_DD = 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%, T_A = –40 to 85 ºC)
Parameter
Supply Current (Supply
current is independent of
V_DD)
CKIN Input Pin
Symbol
I_DD
Test Condition
LVPECL Format
622.08 MHz Out
All CKOUTs Enabled¹
LVPECL Format
622.08 MHz Out
Only 1 CKOUT Enabled¹
CMOS Format
19.44 MHz Out
All CKOUTs Enabled²
CMOS Format
19.44 MHz Out
Only CKOUT1 Enabled²
Min Typ Max Units
—
251 279
mA
—
217 243
mA
—
204 234
mA
—
194 220
mA
Input Common Mode
Voltage
(Input Threshold Voltage)
V_ICM
Input Resistance
Input Voltage Level Limits
Single-ended Input Voltage
Swing
CKN_RIN
CKN_VIN
V_ISE
1.8 V ± 5%
2.5 V ± 10%
3.3 V ± 10%
Single-ended
See note ³
f_CKIN < 212.5 MHz
See Figure 2.
0.9
—
1.4
V
1.0
—
1.7
V
1.1
—
1.95
V
20
40
60
k
0
—
V_DD
V
0.2
—
—
V_PP
f_CKIN > 212.5 MHz
See Figure 2.
0.25
—
—
V_PP
Notes:
1. LVPECL outputs require VDD > 2.25 V.
2. This is the amount of leakage that the 3L inputs can tolerate from an external driver. See Figure 3 on page 9. In most
designs, an external resistor voltage divider is recommended.
3. No overshoot or undershoot.
4
Preliminary Rev. 0.15