SI5317 Datasheet, PDF(11/50 Page) Silicon Laboratories – Pin-Controlled 1

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SI5317 Datasheet, PDF (11/50 Pages) Silicon Laboratories – Pin-Controlled 1_710 MHz Jitter Cleaning Clock

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Si5317

Table 4. AC Characteristics (Continued)

(VDD = 1.8 Â±5%, 2.5 Â±10%, or 3.3 V Â±10%, TA = â40 to 85 ÂºC)

Parameter

Symbol

Test Condition

Min

LVCMOS Output Pins

Rise/Fall Times

tRF

CLOAD = 20 pf

See Figure 2

LOSn Trigger Window

Time to Clear LOS Alarm

LOSTRIG From LVST CKINï to LOSï

Measured from appearance 90

tLOSCLR of valid CKIN to ï¯ï of LOS

alarm

Time to Clear LOL after LOS Cleared tCLRLOL fin unchanged and XA/XB â

stable.

ï¯ï LOS to ï¯ LOL

PLL Performance

Lock Time

tLOCKHW ïï RST with valid CKIN to ï¯ï â

LOL; BW = 100 Hz

Closed Loop Jitter Peaking

Jitter Tolerance

JPK

JTOL

BW determined by

BWSEL[1:0]

5000/

Minimum Reset Pulse Width

Lock Time

Spurious Noise

tRSTMIN

tLOCKMP Reset b ï to ï¯ of LOL

SPSPUR

Max spur @ n x f3

(n > 1, n x f3 < 100 MHz)

Typ

0.05

Max Units

750 Âµs

220 ms

1.2 sec

0.1

1000

â75

ns pk-

Âµs

dBc

Preliminary Rev. 0.15

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