SI5317 Datasheet, PDF (12/50 Pages) Silicon Laboratories – Pin-Controlled 1_710 MHz Jitter Cleaning Clock

Si5317
Table 5. Performance Specifications^{1, 2, 3, 4, 5}
(V_DD = 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%, T_A = –40 to 85 ºC)
Parameter
Symbol
Test Condition
Min
Typ
Max Unit
Jitter Generation
f_IN = f_OUT = 622.08 MHz,
LVPECL output format
BW = 120 Hz
J_GEN
50 kHz–80 MHz
12 kHz–20 MHz
800 Hz–80 MHz
—
0.32
0.42 ps rms
—
0.31
0.41 ps rms
—
0.4
0.45 ps rms
Phase Noise
CKO_PN
f_IN = f_OUT = 622.08 MHz
LVPECL output format
100 Hz offset
1 kHz offset
10 kHz offset
—
–65
— dBc/Hz
—
–95
— dBc/Hz
—
–110
— dBc/Hz
100 kHz offset
—
–117
— dBc/Hz
1 MHz offset
—
–130
— dBc/Hz
Notes:
1. BWSEL [1:0] loop bandwidth settings provided in Table 9 on page 22.
2. 114.285 MHz 3rd OT crystal used as XA/XB input.
3. V_DD = 2.5 V
4. T_A = 85 °C
5. Test condition: f_IN = 622.08 MHz, f_OUT = 622.08 MHz, LVPECL clock input: 1.19 Vppd with 0.5 ns rise/fall time
(20-80%), LVPECL clock output.
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Preliminary Rev. 0.15