SI5317 Datasheet, PDF(28/50 Page) Silicon Laboratories – Pin-Controlled 1

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SI5317 Datasheet, PDF (28/50 Pages) Silicon Laboratories – Pin-Controlled 1_710 MHz Jitter Cleaning Clock

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Si5317

4.2. Output Clock Driver

The Si5317 has a flexible output driver structure that can drive a variety of loads, including LVPECL, LVDS, CML,

and CMOS formats. The signal format is selected for CKOUT output using the SFOUT [1:0] pins. This modifies the

output common mode and differential signal swing. See Table 2, âDC Characteristicsâ for output driver

specifications. The SFOUT [1:0] pins are three-level input pins with the states designated as L (ground), M (VDD/2),

and H (VDD). Table 12 shows the signal formats based on the supply voltage and the type of load being driven.

Table 12. Output Signal Format Selection (SFOUT)

SFOUT[1:0]

Signal Format

CML

LVDS

CMOS

Disabled

LVPECL

Low-swing LVDS

All Others

Reserved

Si5317

CKOUTn

Z0 = 50 ï

100 ï

Rcvr

Figure 12. Typical Differential Output Circuit

Si5317

CKOUTn

CMOS

Logic

Optionally Tie CKOUTn

Outputs Together for Greater Strength

Figure 13. Typical CMOS Output Circuit (Tie CKOUTn+ and CKOUTnâ Together)

For the CMOS setting (SFOUT = LH), both output pins drive single-ended in-phase signals and should be

externally shorted together to obtain the drive strength specified in Table 2, âDC Characteristicsâ.

Preliminary Rev. 0.15

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