SI5317 Datasheet, PDF (36/50 Pages) Silicon Laboratories – Pin-Controlled 1_710 MHz Jitter Cleaning Clock

Si5317
7. Typical Phase Noise Plots
The following is a typical phase noise plot. The clock input source was a Rohde and Schwarz model SML03 RF
Generator. The phase noise analyzer was an Agilent model E5052B. The Si5317 operates at 3.3 V with an ac
coupled differential PECL output and an ac coupled differential sine wave input from the RF generator at 0 dBm.
Note that, as with any PLL, the output jitter that is below the loop BW is caused by the jitter at the input clock. The
loop BW was 120 Hz.
7.1. Example: SONET OC-192
Figure 22. Typical Phase Noise Plot
Jitter Band
SONET_OC48, 12 kHz to 20 MHz
SONET_OC192_A, 20 kHz to 80 MHz
SONET_OC192_B, 4 to 80 MHz
SONET_OC192_C, 50 kHz to 80 MHz
Brick Wall, 800 Hz to 80 MHz
Jitter, RMS
250 fs
274 fs
166 fs
267 fs
274 fs
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Preliminary Rev. 0.15