SI5317 Datasheet, PDF(6/50 Page) Silicon Laboratories – Pin-Controlled 1

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SI5317 Datasheet, PDF (6/50 Pages) Silicon Laboratories – Pin-Controlled 1_710 MHz Jitter Cleaning Clock

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Si5317

Table 2. DC Characteristics (Continued)

(VDD = 1.8 Â±5%, 2.5 Â±10%, or 3.3 V Â±10%, TA = â40 to 85 ÂºC)

Parameter

Symbol

Test Condition

Min Typ Max Units

Output Short to VDD

CKOISC+

VDD = 3.63 V

CML, LVDS, LVPECL

VDD = 1.89 V

CML, LVDS

VDD = 3.63 V

CMOS

190 200

VDD = 1.89 V

CMOS

Differential Output

Resistance

Common Mode Output

Resistance (to VDD)

CKORD

CKORCM

Disable

CML, LVPECL, LVDS,

Disable

CML, LVPECL, LVDS

Disable

1.5

ÂµA

170 200 230

100 115

Mï

Output Voltage Low

Output Voltage High

CKOVOLLH

CKOVOHLH

CMOS

VDD = 1.71 V

CMOS

0.4

0.8 x VDD â

Output Drive Current

CKOIO

CMOS

Driving into CKOVOL for out-

put low or CKOVOH for output

high. CKOUT+ and CKOUTâ

shorted externally.

2-Level LVCMOS Input Pins

VDD = 1.71 V

VDD = 2.97 V

7.5

Input Voltage Low

VIL

VDD = 1.71 V

0.5

VDD = 2.25 V

0.7

VDD = 2.97 V

0.8

Input Voltage High

VIH

VDD = 1.89 V

1.4

VDD = 2.25 V

1.8

VDD = 3.63 V

2.5

Input Low Current

IIL

ÂµA

Input High Current

IIH

ÂµA

Weak Internal Input Pull-up

Resistor

RPUP

kï

Notes:

1. LVPECL outputs require VDD > 2.25 V.

2. This is the amount of leakage that the 3L inputs can tolerate from an external driver. See Figure 3 on page 9. In most

designs, an external resistor voltage divider is recommended.

3. No overshoot or undershoot.

Preliminary Rev. 0.15

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