SI5317 Datasheet, PDF (38/50 Pages) Silicon Laboratories – Pin-Controlled 1_710 MHz Jitter Cleaning Clock

Si5317
9. Pin Descriptions: Si5317
36 35 34 33 32 31 30 29 28
RST 1
27 FRQSEL3
FRQTBL 2
26 FRQSEL2
LOS 3
25 FRQSEL1
NC 4
VDD 5
XA 6
GND
Pad
24 FRQSEL0
23 BWSEL1
22 BWSEL0
XB 7
21 _NC
GND 8
20 DEC
NC 9
19 INC
10 11 12 13 14 15 16 17 18
Note: Pin assignments are preliminary and subject to change.
Table 15. Si5317 Pin Descriptions
Pin #
1
2
3
5, 10, 32
Pin Name
RST
FRQTBL
LOS
V_DD
I/O Signal Level
Description
I
LVCMOS External Reset.
Active low input that performs external hardware reset of
device. Resets all internal logic to a known state. Clock out-
puts are tristated during reset. After rising edge of RST sig-
nal, the Si5317 will perform an internal self-calibration when
a valid input signal is present.
This pin has a weak pull-up.
I
3-level Frequency Table.
Selects frequency table.
This pin has a weak pull-up and weak pull-down and defaults
to M. Some designs may require an external resistor voltage
divider when driven by an active device that will tri-state.
O LVCMOS CKIN Loss of Signal.
Active high loss-of-signal indicator for CKIN. Once triggered,
the alarm will remain active until CKIN is validated.
0 = CKIN present
1 = LOS on CKIN
V_DD
Supply Supply.
The device operates from a 1.8, 2.5, or 3.3 V supply. Bypass
capacitors should be associated with the following V_DD pins:
5
0.1 µF
10
0.1 µF
32
0.1 µF
A 1.0 µF should also be placed as close to device as is
practical.
38
Preliminary Rev. 0.15