SI5317 Datasheet, PDF (7/50 Pages) Silicon Laboratories – Pin-Controlled 1_710 MHz Jitter Cleaning Clock

Si5317
Table 2. DC Characteristics (Continued)
(V_DD = 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%, T_A = –40 to 85 ºC)
Parameter
Weak Internal Input
Pull-down Resistor
3-Level Input Pins
Symbol
R_PDN
Test Condition
Min Typ Max Units
—
75
—
k
Input Voltage Low
Input Voltage Mid
Input Voltage High
Input Low Current
Input Mid Current
Input High Current
LVCMOS Output Pins
V_ILL
V_IMM
V_IHH
I_ILL2
I_IMM2
I_IHH2
—
— 0.15 x V_DD V
0.45 x V_DD — 0.55 x V_DD V
0.85 x V_DD —
—
V
–20
—
—
µA
–2
—
2
µA
—
—
20
µA
Output Voltage Low
V_OL
I_O = 2 mA
—
—
0.4
V
V_DD = 1.62 V
I_O = 2 mA
V_DD = 2.97 V
—
—
0.4
V
Output Voltage High
V_OH
I_O = –2 mA
V_DD = 1.62 V
V_DD – 0.4 —
—
V
I_O = –2 mA
V_DD = 2.97 V
V_DD – 0.4 —
—
V
Single-Ended Reference Clock Input Pin XA (XB with cap to gnd)
Input Resistance
XA_RIN
XTAL/RefCLK
8.5
10
11.5
k
Input Voltage Level Limits
XA_VIN
RATE[1:0] = LM, ML, MH, or
HM
0
—
1.2
V
Input Voltage Swing
XA_VPP
0.5
—
1.2
V_PP
Differential Reference Clock Input Pins (XA/XB)
Input Resistance
XA/XB_RIN
XTAL/RefCLK
8.5
10
11.5
k
Differential Input Voltage
Level Limits
XA/XB_VIN
RATE[1:0] = LM, ML, MH, or
HM
0
—
1.2
V
Input Voltage Swing
XA_VPP/XB_VPP
0.5
—
1.2 V_{PP, each}
Notes:
1. LVPECL outputs require VDD > 2.25 V.
2. This is the amount of leakage that the 3L inputs can tolerate from an external driver. See Figure 3 on page 9. In most
designs, an external resistor voltage divider is recommended.
3. No overshoot or undershoot.
Preliminary Rev. 0.15
7