SI5317 Datasheet, PDF (40/50 Pages) Silicon Laboratories – Pin-Controlled 1_710 MHz Jitter Cleaning Clock

Si5317
Pin #
23
22
27
26
25
24
29
28
33
30
34
35
Pin Name
BWSEL1
BWSEL0
FRQSEL3
FRQSEL2
FRQSEL1
FRQSEL0
CKOUT1–
CKOUT1+
SFOUT0
SFOUT1
Table 15. Si5317 Pin Descriptions (Continued)
I/O Signal Level
Description
I
3-Level Loop Bandwidth Select.
Three level inputs that select the DSPLL closed loop band-
width. See Table 9 on page 22 for available settings.
These pins have both weak pull-ups and weak pull-downs
and default to M.
Some designs may require an external resistor voltage
divider when driven by an active device that will tri-state.
Frequency Select.
Three level inputs that select the input clock and clock range.
See Table 9 on page 22.
These pins have both weak pull-ups and weak pull-downs
and default to M.
Some designs may require an external resistor voltage
divider when driven by an active device that will tri-state.
O
Multi
Clock Output 1.
Output signal format is selected by SFOUT pins. Differential
formats supported for LVPECL, LVDS, and CML compatible
modes. For single-ended CMOS format, both output pins
drive identical, in-phase clock outputs.
I
3-Level Signal Format Select.
Three-level inputs that select the output signal format (com-
mon mode voltage and differential swing) for both CKOUT1
and CKOUT2.
CKOUT2–
O
CKOUT2+
Multi
SFOUT[1:0]
Signal Format
HH
Reserved
HM
LVDS
HL
CML
MH
LVPECL
MM
Reserved
ML
LVDS—Low Swing
LH
CMOS
LM
Disable
LL
Reserved
These pins have both weak pull-ups and weak pull-downs
and default to M.
Some designs may require an external resistor voltage
divider when driven by an active device that will tri-state.*
Clock Output 2.
Output signal format is selected by SFOUT pins. Differential
formats supported for LVPECL, LVDS, and CML compatible
modes. For single-ended CMOS format, both output pins
drive identical, in-phase clock outputs.
40
Preliminary Rev. 0.15