SI5317 Datasheet, PDF (25/50 Pages) Silicon Laboratories – Pin-Controlled 1_710 MHz Jitter Cleaning Clock

Si5317
4. High-Speed I/O
4.1. Input Clock Buffer
The Si5317 provides differential inputs for the CKIN clock input. This input is internally biased to a common mode
voltage (see Table 2, “DC Characteristics”) and can be driven by either a single-ended or differential source. No
additional external bias is required. Figure 7 through Figure 10 shows typical interface circuits for LVPECL, CML,
LVDS, or CMOS input clocks. Note that the jitter generation improves for higher levels on CKINn within the limits in
Table 4, “AC Characteristics”.
AC coupling the input clocks is recommended because it removes any issue with common mode input voltages.
However, either ac or dc coupling is acceptable. Figure 7 and Figure 8 shows various examples of different input
termination arrangements. Unused inputs can be left unconnected.
3.3 V
130  130 
C
LVPECL
Driver
82  82 
C
Si5317
40 k
40 k
CKIN +
300 
CKIN ^_
± ^VICM
Figure 7. Differential LVPECL Termination
3.3 V
130 
C
Driver
82 
C
Si5317
40 k
40 k
CKIN +
300 
CKIN ^_
± ^VICM
Figure 8. Single-ended LVPECL Termination
Preliminary Rev. 0.15
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