SI5317 Datasheet, PDF (41/50 Pages) Silicon Laboratories – Pin-Controlled 1_710 MHz Jitter Cleaning Clock

Si5317
Table 15. Si5317 Pin Descriptions (Continued)
Pin #
Pin Name I/O Signal Level
Description
4,9,12,13,
NC
—
—
No Connect.
21,36
Leave floating. Make no external connections to this pin for
normal operation.
GND PAD
GND
GND Supply Ground Pad.
The ground pad must provide a low thermal and electrical
impedance to a ground plane.
*Note: LVPECL requires VDD > 2.25 V
Preliminary Rev. 0.15
41