SI5317 Datasheet, PDF (37/50 Pages) Silicon Laboratories – Pin-Controlled 1_710 MHz Jitter Cleaning Clock

8. Typical Application Circuit
Si5317
System
Power
Supply
Ferrite
Bead
VDD = 3.3 V
130 
Input Clock¹
82 
130 
82 
CKIN+
CKIN–
C4 1 µF
C3 0.1 µF
C2 0.1 µF
C1 0.1 µF
CKOUT1+
CKOUT1–
SFOUT[1:0]²
CKOUT2+
CKOUT2–
0.1 µF
+
100 
–
0.1 µF
Clock Outputs
VDD
15 k
15 k
Signal Format Select
0.1 µF
100 
LOS
LOL
Option 1:
XA
Crystal
XB
Option 2:
Ext. Refclk+
Ext. Refclk–
Crystal/Ref Clk
0.1 µF
0.1 µF
VDD
15 k
15 k
XA
XB
RATE[1:0]²
Si5317
VDD
Frequency Table
FRQTBL³
CKIN Loss of Signal Indicator
PLL Loss of Lock Indicator
VDD
15 k
Frequency Select
VDD 15 k
15 k
Bandwidth Select
15 k
Skew Increment
FRQSEL[3:0]²
BWSEL[1:0]²
INC
Skew Decrement
Clock Output 2 Disable/
Bypass Mode Control
Reset
DEC
DBL2_BY²
RST
Notes:
1. Assumes differential LVPECL termination (3.3 V) on clock inputs.
2. Denotes tri-level input pins with states designated as L (ground), M (VDD/2), and H (VDD).
3. For schematic and layout examples, refer to Si5317-EVB User Manual.
Figure 23. Si5317 Typical Application Circuit
Preliminary Rev. 0.15
37