SI5317 Datasheet, PDF (24/50 Pages) Silicon Laboratories – Pin-Controlled 1_710 MHz Jitter Cleaning Clock

Si5317
3.6. PLL Bypass Mode
The Si5317 supports a PLL bypass mode in which the selected input clock is fed directly to both enabled output
buffers, bypassing the DSPLL. Internally, the bypass path is implemented with high-speed differential signaling;
however, this path is not a low jitter path and will see significantly higher jitter on CKOUT. In PLL bypass mode, the
input and output clocks will be at the same frequency. PLL bypass mode is useful in a laboratory environment to
measure system performance with and without the jitter attenuation provided by the DSPLL. The DSBL2_BY pin is
used to select the PLL Bypass Mode according to Table 11.
Table 11. DSBL2/BYPASS Pin Settings
DSBL2/BYPASS
L
M
H
Function
CKOUT2 Enabled
CKOUT2 Disabled
PLL Bypass Mode w/ CKOUT2 Enabled
External Crystal or
Reference Clock
RATE[1:0]
XB
XA
PLL Bypass
CKIN+
CKIN–
LOS
LOL
RST
BWSEL[1:0]
FRQSEL[3:0]
FRQTBL
INC
DEC
2
f3
Alarms
Control
Bandwidth
Control
Frequency
Control
Skew Control
DSPLL^®
0
fOSC
1
0
1
2
CKOUT+
CKOUT–
SFOUT[1:0]
2
CKOUT+
CKOUT–
Voltage
Regulator with
High PSRR
DBL2_BY
VDD (1.8, 2.5, or 3.3 V)
GND
Figure 6. Bypass Signal
24
Preliminary Rev. 0.15