SI5317 Datasheet, PDF (14/50 Pages) Silicon Laboratories – Pin-Controlled 1_710 MHz Jitter Cleaning Clock

Si5317
2. Functional Description
External Crystal or
Reference Clock
RATE[1:0]
XB
XA
CKIN+
CKIN–
LOS
LOL
RST
BWSEL[1:0]
FRQSEL[3:0]
FRQTBL
INC
DEC
2
f3
Alarms
Control
Bandwidth
Control
Frequency
Control
Skew Control
DSPLL^®
fOSC
2
CKOUT+
CKOUT–
SFOUT[1:0]
2
CKOUT+
CKOUT–
DBL2_BY
Voltage
Regulator with
High PSRR
VDD (1.8, 2.5, or 3.3 V)
GND
Figure 5. Detailed Block Diagram
2.1. Overview
The Si5317 is a 1:1 jitter-attenuating precision clock for applications requiring sub 1 ps jitter performance. The
Si5317 accepts one clock input ranging from 1 to 710 MHz and generates two clock outputs at the same frequency
ranging from 1 to 710 MHz. The Si5317 is based on Silicon Laboratories' 3rd-generation DSPLL® technology,
which provides jitter attenuation on any frequency in a highly integrated PLL solution that eliminates the need for
external VCXO and loop filter components. The nominal operating frequency is selectable from a look-up table.
The Si5317 PLL loop bandwidth (BW) is selectable via the BWSEL[1:0] pins and supports a range from 60 Hz to
8.4 kHz.
The Si5317 monitors the input clock for loss-of-signal (LOS) and provides a LOS alarm when it detects missing
pulses on the input clock. The device monitors the lock status of the DSPLL. The lock detect algorithm works by
continuously monitoring the phase of the input clock in relation to the phase of the feedback clock.
The Si5317 provides a VCO freeze capability that allows the device to continue generation of a stable output clock
when the selected input clock is lost. During VCO freeze, the DSPLL latches its VCO settings and uses its XA/XB
clock as its frequency reference.
The Si5317 has two output clock drivers and can be configured as four single-ended or two differential outputs.
The signal format of the clock output is selectable to support LVPECL, LVDS, CML, or CMOS loads. The device
operates from a single 1.8, 2.5, or 3.3 V supply. The use of LVPECL requires a VDD > 2.25 V.
14
Preliminary Rev. 0.15