SH3100 Datasheet, PDF (78/80 Pages) Semtech Corporation – Supervisory IC with I2C Interface and PWM

SH3100
POWER MANAGEMENT
Functional Descriptions (continued)
HFDCO Clock On/Off Control
The HFDCO automatically starts up at the programmed
rate after power-up. It may then be turned off and on by
I²C access or by CLKIN control. To use CLKIN for On/Off
control, activity needs to be detected on CLKIN after the
clock output starts on CLK0. This places the SH3100 into
AutoClkDetect mode which turns off the clock once it de-
tects that four consecutive cycles of CLKIN are missing. In
this mode, the clock is restarted within 2μs once a single
transition is detected on CLKIN.
The SH3100 defaults to non-AutoClkDetect mode until
activity has been sensed on CLKIN. When not in AutoClk-
Detect mode, CLK0 can be disabled by clearing the ClkEn
bit of the Config register, but only once at least one inter-
rupt source has been programmed. This is a protection
mechanism to prevent the microcontroller from killing its
own clock without setting up the Interrupt with which it
can be restarted. CLK0 restarts when the Interrupt event
occurs.
The advantage of CLKIN clock control is that it is much
faster than I²C access and it fits well with the clock STOP
facility of many microcontrollers which use internal gat-
ing to disable their own crystal oscillators. In this case
CLK0 should be connected to the microcontroller XIN and
CLKIN to the XOUT.
In AutoClkDetect mode, CLK0 is stopped at the same po-
larity as CLKIN. This allows for microcontroller implemen-
tations where the microcontroller XOUT is disabled using
either a NAND or a NOR gate. To maintain CLK0 active,
CLKIN must be synchronous with CLK0, but phase is not
important. In non-AutoClkDetect mode, CLK0 is stopped
in the High state.
AutoClkDetect mode is disabled on reset, and remains so
until activity is first seen on CLKIN. When not in AutoClk-
Detect mode, the write access to the CLK0Config register
(which disables the clock) must adhere to the following
timing constraint:
The time TDO-STOP from the falling edge of SCL clocking
in the last data bit D0 to the rising edge of SDA marking
the I²C STOP condition must not exceed (1024*CLK0
periods) or (4*SCL periods), whichever is less.
CLK0 is stopped TD0-CLKOFF following the falling edge of
SCL clocking in the last data bit D0. This time equates to
4*SCL periods or 1024*CLK0, whichever is less.
CLK0
T_D0-STOP
SCL ^...
...
SDA
WD3
WD2
WD1
WD0
Write data
T_DO-CLKOFF
© 2006 Semtech Corp.
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