SH3100 Datasheet, PDF (73/80 Pages) Semtech Corporation – Supervisory IC with I2C Interface and PWM

POWER MANAGEMENT
Functional Descriptions (continued)
Write to single register (combined format)
SCL
SDA
SA SA SA
210
R/
W
Slave address (3 LSBs
determined by
I2CSlaveAddr register)
RA RA RA RA RA RA RA RA
76543210
Register Address
SH3100
SCL may be briefly held low
(stretched) by SH3100 here
SA SA SA
210
0
R/
W
Slave address (3 LSBs
determined by
I2CSlaveAddr register)
WD WD WD WD WD WD WD WD
76543210
Write Data
Write to single register ('normal' format)
SCL
SDA
SA2 SA1 SA0
Slave address (3 LSBs
determined by I2CSlaveAddr
register)
R/W
SCL may be briefly held low
(stretched) by SH3100 here
RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0
WD7 WD6 WD5 WD4 WD3 WD2 WD1 WD0
Register Address
Write Data
Read from single register (combined format)
SCL
SCL may be briefly held low
(stretched) by SH3100 here
SDA
SA SA SA
210
R/
W
Slave address (3 LSBs
determined by
I2CSlaveAddr register)
RA RA RA RA RA RA RA RA
76543210
Register Address
SA SA SA
210
R/
W
Slave address (3 LSBs
determined by
I2CSlaveAddr register)
RD RD RD RD RD RD RD RD
76543210
Read data driven by SH3100
SDA and SCL are driven by the Master unless otherwise specified.
SAn = Slave Address (bit n)
RAn = Register Address (bit n)
WDn = Write Data (bit n)
RDn = Read Data (bit n)
I²C Timing Diagrams
© 2006 Semtech Corp.
73
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