SH3100 Datasheet, PDF(74/80 Page) Semtech Corporation – Supervisory IC with I2C Interface and PWM

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SH3100 Datasheet, PDF (74/80 Pages) Semtech Corporation – Supervisory IC with I2C Interface and PWM

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SH3100

POWER MANAGEMENT

Functional Descriptions (continued)

High-Frequency Digitally-Controlled Oscillator (HFDCO)

The master HF oscillator is a 19-bit high-frequency digi-

tally-controlled oscillator (HFDCO) which can either free-

run or be controlled within a Frequency Locked Loop (FLL)

locked to the 32.768kHz crystal clock.

The HFDCO is guaranteed to operate over the range 8MHz

to 33.5MHz with approximately 2 kHz resolution.

When free-running, the frequency stays stable to within

Â±0.5% over 0ÂºC to 70ÂºC and within Â±1% over -40ÂºC to

+85ÂºC. When FLL locks to the crystal, the frequency has

the same stability as the crystal.

On a programmed device, the start-up code for the HFDCO

is programmed into the register at 25Â°C.

This means that if the chip initially powers up at 25Â°C,

the oscillator frequency is within Â±0.1% of the desired fre-

quency. If the temperature is not at 25Â°C on power up,

then the frequency is within Â±1% of the desired frequen-

cy. Once the FLL starts (assuming the crystal is present)

the oscillator is pulled exactly into lock. If the chip is then

placed into standby mode at any particular temperature,

the oscillator stops, but the control code determined by

the FLL is maintained, such that if the oscillator is then

started up at the same temperature, the accuracy is with-

in Â±0.1% of the desired frequency.

In order to achieve a frequency resolution of 2kHz over

the required range, a linear DCO would require approxi-

mately 14 bits of adjustment resolution. To achieve this

with a single linear monotonic system is impractical due

to component mismatch, therefore an intentionally non-

monotonic system is used. This is made up from a num-

ber of overlapping frequency banks such that it is guaran-

teed that every frequency between 8MHz and 33.5MHz

can be achieved. This results in a net 19-bit control code,

of which the 16 bits stored in the register are sufï¬cient for

start-up programming.

There is sufï¬cient bank overlap built into the system to

ensure that while the FLL is running, drift in the control

code due to temperature variations does not result in the

code rolling over a bank boundary and thus requiring a

large delay while the FLL loop recovers from the bank

rollover. There is also additional protection built in such

that if a range rollover point is reached, then the control-

ling logic detects this and jumps the LSB bank code to

the appropriate point to give the theoretically correct fre-

quency for the next bank. In practice, due to component

mismatch, the new frequency may not be exactly correct,

and the FLL would need a few more cycles to settle to the

correct point.

Note 1: If there is no crystal present, the FLL is not automati-

cally enabled, as there is no point in locking to the internal

32.768kHz oscillator, since the HFDCO free-running accuracy

is higher than that of the internal oscillator.

Note 2: Due to process variations, there is no ï¬xed correlation

between control code and frequency therefore the start-up

code is determined on test and uniquely programmed in to the

registers for each device.

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