SH3100 Datasheet, PDF (59/80 Pages) Semtech Corporation – Supervisory IC with I2C Interface and PWM

SH3100
POWER MANAGEMENT
Functional Descriptions (continued)
System Reset - Watchdog Timer (WDT)
System Reset - Manual Override
The watchdog is the other dedicated supervisory function
that manages the micro controller reset. Once enabled, it
requires the micro controller to alternately write two unique
codes (0x5A, 0xC3) to the WDTCode register. Failure to
write the correct code before the timer expires causes
a reset, as does writing an invalid code. This function is
disabled on power-up, and is only enabled once it has
been initialized.
Note: Once enabled, the WDT cannot be disabled.
By default (non AutoWDTSuspend mode), the watchdog
runs at a rate determined by the WDTPrescaler register,
either 128Hz, 64, 32 or 16Hz, and counts up to a maxi-
mum of 128 counts, which relates to a maximum timeout
period of 1, 2, 4 or 8 seconds respectively.
In order to prevent the WDT from timing out while the pro-
cessor is legitimately asleep for a long period, the WDT
can be optionally set (by setting the AutoWDTSuspend
bit of the Config register) to be divided down from CLK0,
instead of from the default selected 32.768kHz source.
In this mode the WDT counter counts processor cycles,
rather than real time, and can be set for a timeout pe-
riod of between 256 and 262144 processor cycles deter-
mined by WDTPeriod and WDTPreScaler. This means that
the watchdog function sleeps while the HFDCO clock is in
standby.
A system reset can be manually triggered by momen-
tarily pulling down the NRST pin. This is detected by the
SH3100, which then holds NRST low for the programmed
reset duration. After the reset period ends, NRST is re-
leased and pulled high by the internal 20KΩ pullup.
To correctly detect a manual reset, the NRST pin should
be pulled low for a period of at least 50ns. This can be
achieved by adding a 47pF capacitor to ground on the
NRST pin. This gives an effective RC rise time on NRST of
1μs, which is sufficient to ensure that NRST stays low for
long enough to be detected, even if initially held low for
only 1ns.
Note 1: If manual reset is triggered by a momentary pulldown
on NRST, the start-up sequence timer can not start until after
a time equal to the programmed reset duration has elapsed.
This means that for very short manual reset events, the ob-
served reset duration on NRST appears to be double the pro-
grammed reset duration
Note 2: If manual reset is held low for longer than twice the
programmed reset duration, then when it is released, NRST
rises back to VDD with no further delay.
Note 3: A reset of this type sets the Brownout Event status
flag.
The AutoWDTSuspend register bit can only be written to
prior to WDT initialization. When the WDT times out, the
cause can be identified by reading the CauseOfReset reg-
ister.
© 2006 Semtech Corp.
59
www.semtech.com