SH3100 Datasheet, PDF (71/80 Pages) Semtech Corporation – Supervisory IC with I2C Interface and PWM

SH3100
POWER MANAGEMENT
Functional Descriptions (continued)
I²C Interface
The I²C interface conforms to the 400kHz fast-mode of • SH3100 generates an ACK pulse, and may stretch
the 2000 Philips I²C specification, acting as a slave only.
SCL by holding it low for up to two periods of CLK0, if
Both SCL and SDA pins are dedicated. The maximum fre-
CLK0 is relatively slow compared to SCL
quency of the I²C interface is determined by the strength
of the external pull-up on SCL and SDA, and there is no ^{• Stop condition (rising edge on SDA while SCL is high)}
minimum frequency.
The seven-bit I²C Slave Address is 0100xxx, and the three
LSBs are programmed into the register. Both read and
ite protocols can use the I²C combined format, and addi-
tionally, the write protocol can support the non-combined
(‘normal’) format.
Normal Write Format
• Start condition (falling edge on SDA while SCL is high)
to commence the access to write the register address
to the SH3100
Combined Write Format
• 7-bit slave address on SDA, clocked in by SCL
• Start condition (falling edge on SDA while SCL is high)
to commence the access to write the register address to
the SH3100
• 1-bit read/write indicator, set low because the follow-
ing 8 bits are the register address, written into the
SH3100
• 7-bit slave address on SDA, clocked in by SCL 1-bit • SH3100 generates ACK pulse to acknowledge slave
read/write indicator, set low because the follow-
address
ing 8 bits are the register address, written into the
SH3100
• 8-bit register address
• SH3100 generates ACK pulse to acknowledge slave _{• SH3100 generates ACK pulse to confirm register ad-}
address
dress transfer
• 8-bit register address
• The microcontroller generates 8-bit write data
• SH3100 generates ACK pulse to confirm register ad- _{• SH3100 generates an ACK pulse, and may stretch}
dress transfer
SCL by holding it low for up to two periods of CLK0, if
• Restart condition to commence the access to write
CLK0 is relatively slow compared to SCL
payload data to the register address set up by the last
access
• Stop condition (rising edge on SDA while SCL is high)
• 7-bit slave address
• 1 bit read/write indicator, set low because the follow-
ing 8 bits are the write data (payload)
• SH3100 generates ACK pulse to acknowledge slave
address
• The microcontroller generates 8-bit write data
© 2006 Semtech Corp.
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